In known methods for producing a bipolar transistor, a base terminal, an emitter terminal and a collector terminal are created on a substrate. While doing so, during processing, the emitter terminal is configured to be clearly higher than the other terminals, such as the base terminal or a gate terminal. If, in particular, several bipolar transistors and/or several bipolar and field-effect transistors are produced on a substrate, this gives rise to the problem of efficiently contacting the respective terminals on the grounds of the emitter terminal being configured to be higher in each case.
FIG. 1 shows a semiconductor device having a substrate 101, a collector contact 103, a base contact 105 and an emitter contact 107, as are known from the prior art. A bipolar-transistor area is shown to the left of the vertical line drawn, and a CMOS area is shown to the right of the line. For producing the semiconductor device shown in FIG. 1, the substrate 101 is initially provided, wherein the collector contact 103 is formed. In a further process step, the base contact 105 is formed on substrate 101, and the emitter contact is produced, for example, on a portion of the base contact. After the end of the process, all devices are covered FEOL (front end of line) with a thin nitride liner and constantly, for example, with a BPSG layer (BPSG=boron phosphor silicate glass) 109, which layer will be polished back to a target thickness so as to planar in a further process step. For contacting contacts 105, 107 and 103, contact vias (CT) are etched into the BPSG until the respective terminal is reached, and are filled with tungsten, for example, after a liner deposition. The electrical contact of the transistors is therefore effected via the contact vias 111, 113 and 115 filled with tungsten. The etching is performed in two steps: Initially, the BPSG is fully etched, whereupon a portion of the nitride liner is recessed. In a further process step, a first structured metal plane 117 is applied to contact vias 111, 113 and 115 filled with tungsten, with which metal plane 117 a contacting of the respective contacts 111, 113, 115 is now produced in a plane. In a further process step, filling-up with oxide and planarization are performed, and further contact vias are etched up to the first metal plane 117 and filled up with tungsten. A second structured metal plane 125 which serves to contact the respective terminals 105, 107 and 103 is formed on the vias 119, 121 and 123 filled with tungsten.
If, additionally, a field-effect transistor is integrated on the substrate, a gate terminal (not shown in FIG. 1) will be integrated on a gate polystack 127. The gate polystack 127 is lower than, for example, the emitter contact 107.
Due to the larger height of the emitter contact 107 (emitter stack), a remaining oxide thickness above the emitter contact 107 is too small, in the etching of the contact vias, to achieve a sufficient overall process window. If, for example, too thin a BPSG layer is left over on the emitter contact 107 after the polishing step, the via 111 filled with tungsten may not be sufficiently structured to achieve a sufficiently conductive contact, so that possibly a large transition impedance towards the emitter contact 107 arises.
A further problem occurring in connection with the production of the semiconductor device shown in FIG. 1 is the fact that, due to the differing heights of, e.g., the base contact 105 and the emitter contact 107, there is a need to etch vias having different depths, which inevitably entails differing etching periods of the respective contact vias. If, for example, the contact via to be produced above the emitter contact 107 is etched for too long, a surface of the emitter contact 107 is affected and damaged, so that the contact vias cannot be etched in one pass without previously taking precautionary measures, which results in the manufacturing process becoming more expensive. The requirements placed upon a selectivity of the contact-via etching up to the emitter contact 107, which consists of polysilicon, for example, are very demanding and also reduce the process window in the step of polishing the BPSG, which may be performed, for example, using the CMP method (BPSG CMP), as well as in the subsequent contact-via etching (CT etch). Due to the increased topology requirements, it is the emitter polysilicon which is always most exposed to the etching attack.
A further disadvantage of the semiconductor device shown in FIG. 1 is the fact that additional contact vias 119, 121 and 123 filled with tungsten as well as the second structured metal plane 125 are required for contacting the respective terminals 103, 105 and 107. On the one hand, this leads to an increase in the process costs, on the other hand a complex manufacturing process consisting of a plurality of process steps must be employed for producing the semiconductor device shown in FIG. 1, so that high demands must be placed upon, e.g., the process stability, which renders the manufacturing process even more expensive.
A further disadvantage of the semiconductor device which is in line with the prior art and is shown in FIG. 1 is the fact that the respective contacts 103, 105 and 107 are contacted via a plurality of contact structures, such as vias 111, 113 and 115 filled with tungsten, first metalization plane 117, vias 119, 121 and 123 filled with tungsten, as well as second metalization plane 125, which is why a high contact resistance, for example, may form due to potential contact inaccuracies, which contact resistance contributes to a deterioration of both the electrical properties (e.g. higher power dissipation) and of the performance of the bipolar transistor.
A further disadvantage of the semiconductor device shown in FIG. 1 is to be seen in the fact that due to the second metalization plane 125 and to the vias 119, 121 and 123 filled with tungsten, a spatial expansion of such a semiconductor structure becomes larger in the vertical direction, so that, for example, higher demands must be placed upon the process stability in producing the BPSG layer 109, which renders the manufacturing process even more expensive.
To increase the process window, which is to be evaluated as critical, it is feasible, for example, to limit the BPSG-CMP specification and to reduce the height of the emitter stack 107 a minimum. By doing so, however, the process window for the contact-via etch/etching is restricted to the same extent, since in the case of the emitter stack 107 being too low, the damaging of same caused by an etching process may be severe.
If, for example, bipolar transistors and field-effect transistors are contacted on a substrate, the height of the emitter stack 107 will see a significant increase compared to, for example, a gate terminal of a CMOS transistor (GC polystack) in future bipolar technologies. In this case, even those contact areas which are situated at the lowest location, e.g. source and drain of a field-effect transistor, which are located, as a maximum, at a height of e.g. 900 nm, must be opened reliably, without remainders, and without attacking and damaging an emitter polysilicon of a bipolar transistor.